The invention relates to changing clock frequencies.
In a system, some components may run at core or internal clock frequencies that are higher than the frequency of an external clock (such as a bus clock) to the components. Components may include a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC) a programmable gate array (PGA), or any other device which can run at core speeds many times greater than the bus clock speed. The component's core clock frequency may be at a lower level for power reduction, which may be advantageous in a portable system where battery life is limited. Another advantage may be that system design is simplified by maintaining external clock speeds at lower levels.
In some microprocessors, such as the Pentium.RTM. family of processors from Intel Corporation, the ratio of the core clock frequency to bus clock frequency may be specified at system reset. This ratio may be set using bus fraction data defined by one or more input/output (I/O) pins that are sampled during system reset, for example. The states of the one or more I/O pins may be latched internally on the deactivating edge of a processor reset signal.
Conventionally, the core clock frequency to external clock frequency ratio is set during reset in current processors. Once the clock ratio is set, it remains at that value until the next time the system resets. This may limit the performance level of the system. It is inconvenient to reset the system to change clock frequencies, as the reset process typically may take a relatively long period of time.